In a semiconductor device, circuits having different power source voltages are mounted mixedly. In the case where a plurality of circuits having different power source voltages is mounted, it is preferable to separate power source lines. This case includes a case where both the low (potential) power source lines and the high (potential) power source lines are separated and a case where the low power source lines are connected in common and only the high power source lines are separated. Further, even in the case where the power source voltage is the same, in the circuit, such as an analog circuit, which is vulnerable to the influence of noise, both the power source lines are separated. The circuit portion in which at least the high power source lines are separated is referred to as a domain.
It is known that the semiconductor device is affected by Electro-static discharge (ESD), resulting in the occurrence of damage and an erroneous operation, and therefore, an ESD protection circuit to protect the semiconductor device from discharge is provided. As an ESD model that damages a semiconductor device, there are a test model (human body model:HBM) from an external statically charged object, a test model (charged device model: CDM) by static charge of the semiconductor device itself, etc., and the test method or the like for them are specified. The ESD protection circuit protects a semiconductor device from discharge corresponding to these ESD models. The ESD protection circuit is provided for a wire that is directly connected to an external terminal and for an element that is connected to the wire.
In the case where the semiconductor device has one common high power source line and one common low power source line, it is sufficient to provide the ESD protection circuit at the portion that is connected to the external terminal. However, in the case where the semiconductor device has a plurality of domains, there is such a problem that the signal path between the domains is affected by the ESD and the element of the signal path is damaged. Because of this, for the semiconductor device having a plurality of domains, it is known that the signal path between the domains also needs to be protected in view of the ESD.
In recent years, due to the reduction in power consumption, the power source voltage of the semiconductor device is reduced remarkably, and a phenomenon occurs in which the power source voltage with which desired performance can be obtained in a core (logic) circuit of a semiconductor device differs from chip to chip because of the variation in the process. The range of the power source voltage with which the desired performance can be obtained becomes large, which cannot be ignored, and if the power source voltage is reduced to attain low power consumption, such a problem occurs that the yields of a chip are reduced or the chip does no operate normally. Because of this, the power source voltage with which the desired performance can be obtained in the core circuit is measured for each chip at the time of manufacture, and the actual core circuit is caused to operate on the measured power source voltage. Due to this, a reduction in power consumption and improvement of yields are implemented. In this case, for the circuits other than the core circuit, such as the input or output circuit for an external interface, the PLL circuit, and the analog circuit for which the voltage is specified, the power source voltage is set to a certain voltage, respectively, and is not changed in accordance with the results of the variation in the process. Consequently, for example, the analog circuit is designed so as to operate on a power source voltage of 1.8 V and the core circuit is designed so as to operate on 1.8 V or lower, and the core circuit is caused to operate on an appropriate voltage lower than or equal to 1.8 V, for example, 1.5 V, in accordance with the variation in the process. The technique to change the power source voltage such as this is called the adaptive source voltage (ASV) technique.
In the case where the ASV technique is applied, the power source voltage of the core circuit differs from that of the other circuits, and therefore, it is preferable to separate the power source of each circuit, i.e., to provide a plurality of domains. As described previously, when a plurality of domains is provided, there are a case where both the low (potential) power source lines and the high (potential) power source lines are separated and a case where the low power source lines are connected in common and only the high power source lines are separated. For the circuit that is vulnerable to the influence of noise, such as the analog circuit, both the low power source lines and the high power source lines are separated. The target is a semiconductor device having a plurality of domains, i.e., in which both the low power source lines and the high power source lines are separated.
Further, the signal between the core circuit and the analog circuit is a digital signal and there is a case where no problem occurs even if the signal of the core circuit is input to the analog circuit or the signal of the analog circuit is input to the core circuit, but there is also a case where a level shifter is provided in view of reliability.